Process variation is an increasingly important factor in the design of integrated circuits (ICs) fabricated in advanced semiconductor technologies. Because the precise knowledge of variation is becoming an even more integral part of the design process as technology continues to scale, testing techniques are needed to extract, measure, and characterize variation in a given process and link it to circuit performance.
Process variation in IC fabrication is the deviation from intended or designed values for a structure or circuit parameter of concern. Process variation can result in the fluctuation of parameter values and dimensions in both the structural device and interconnect levels, which can influence the performance of ICs.
In a typical IC manufacturing process, test macros are included in the scribe lines between product chips. Test structures within these scribe line macros may be monitored by physical measurement or electrical test. The data collected may be compared against established limits as part of a process control system. In addition, it is common that certain parametric test macros embedded within product chips are tested during final product test. These product macros may be used to screen parts against established limits. Because one set of data are used for process control while another set are used to screen finished products; differences between the two can lead to false rejects and unanticipated yield loss. Differences in macros design, test conditions, or process, can introduce offsets and reduce the correlation between scribe line data and product data. In advanced semiconductor technologies, characterizing the offsets between these data is a substantial manufacturing challenge.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.